Field of the Invention: The present invention relates to semiconductor devices and methods for fabricating semiconductor devices. More specifically, the invention relates to a method for packaging a semiconductor die having conductive elements that protrude at least to the surface of a covering or encapsulation of the die active surface.
State of the Art: In semiconductor manufacture, a single semiconductor die or chip including a plurality of integrated circuits on an active surface thereof is typically mounted within a sealed package of a silicon-filled epoxy formed thereabout by a process known as transfer-molding. The package generally protects the die from physical damage and from contaminants, such as moisture or chemicals, found in the surrounding environment. The package also provides a lead system for connecting the electrical devices (integrated circuits) formed on the die to a printed circuit board or other higher-level packaging.
Packaged semiconductor dice containing integrated circuits for a broad range of purposes are currently mass produced. Even slight savings in the cost of packaging one such semiconductor die circuit can generate significant overall cost savings to the manufacturer, due to large production volumes, if the reduced-cost packaging affords required package integrity. Further, reduction in package size can eliminate size-based restrictions for use of a die on ever more crowded carrier substrates such as printed circuit boards (PCBs), where available xe2x80x9creal estatexe2x80x9d is at a premium. Therefore, continual cost reductions and quality improvements in the manufacture of these semiconductor packages, while maintaining the overall lateral dimensions of such packages at a reduced size, are of great value in the semiconductor manufacturing field.
In many semiconductor applications, formation of conductive bumps or other external conductive elements on the bond pads of a die is desirable, if not necessary, to connect the die to external conductors. The most common applications where conductive bumps or other elements are used include tape automated bonding (TAB), flip-chip attachment of a die to a carrier substrate, and direct chip attachment (DCA) of a die to a carrier substrate. Conductive bumps may comprise metals or alloys including, without limitation, conventional tin/lead solders, or may comprise conductive or conductor-filled epoxies, all as known in the art. Formation of the conductive bumps used in these applications can be accomplished using a variety of commonly known methods, such as deposition onto bond pads by screening or printing, preform ball or bump placement, or ball bumping using wire bonding equipment to form each individual bump in situ.
A widely practiced way to increase the number of available input/output (I/O) connections for a die is to use flip-chip methodology for packaging, where an array of conductive elements (e.g., conductive bumps, ball bonds, conductive pillars or other conductive structures) is positioned on the active surface or circuit face of the die, which is then mounted active surface down upon a single chip or multi-chip module carrier substrate.
Because of relatively high manufacturing costs associated with state-of the-art metal deposition equipment dedicated specifically to bumping a die for flip-chip attachment, some semiconductor manufacturers have resorted to the aforementioned ball bumping using conventional wire bonding tools (capillaries) to form conductive bumps over the bond pads. In the ball bumping process, a capillary of the wire bonding tool carries a conductive wire toward a bond pad on which a bump is to be formed. A ball is formed at an end of the wire by heating and melting the metal wire. The wire bonding tool capillary then presses the ball against the planar bond pad and the portion of the wire extending past the ball is cut, leaving a ball bump on the bond pad.
A flip-chip or bumped (raised) die is a semiconductor chip (die) having bumps formed on bond pads on the active surface or front side of the die, the bumps being used as electrical and mechanical connectors to conductors of higher level packaging, such as a PCB or other carrier substrate. The bumped die is inverted (flipped) and bonded to trace ends or other terminals on a carrier substrate by means of the bumps. As noted above, diverse materials are conventionally used to form the bumps on the die, such as solder, conductive polymers, and conductor-filled polymers. Typically, if the bumps are solder bumps, solder segments are deposited on the die and then reflowed to form a substantially spherical shape, and subsequently reheated to form a solder joint between the bond pads on the so-called flip-chip and terminal pads on the carrier substrate, the solder joint providing both electrical and mechanical connections between the flip-chip and substrate.
Conventional flip-chip IC devices formed according to the aforementioned fabrication processes exhibit a number of shortcomings. For example, since the active surface of the chip is relatively unprotected, being covered only with a thin passivation layer, damage to the chip can occur during attachment of the chip to the carrier substrate. Likewise, such damage to the chip can occur during handling of the chip or while conducting reliability testing of the same. Moreover, directly bumping the relatively delicate bond pads, even with one or more layers of under-bump metallization thereover to facilitate metallurgical compatibility between the bond pad and the metal bump, may itself cause damage.
As disclosed in U.S. Pat. 5,496,775 to Brooks, encapsulated IC dice having contact bumps have been developed in an attempt to solve some of these problems. In the fabrication process of Brooks, gold balls, which function as leads or contacts, are welded in a stacked or tower fashion onto each bond pad of the IC die. The gold ball tower-bonded die is then placed into a mold and onto a first layer of encapsulation material contained therein. A second layer of encapsulation material is then applied over the tower side of the die, which completely covers the die surface, partially submerging the towers in the encapsulant. The encapsulated IC die is removed from the mold and mounted to tab tape or a PCB, with the nonsubmerged portions of the towers providing an electrical connection thereto. Although these semiconductor packages have solved a number of problems, the fabrication process to form such packages requires numerous fabrication steps and specialized equipment and materials, especially for the creation of the ball towers and the related steps providing encapsulation around the towers. Also, the required formation of stacks of multiple gold balls in the package inevitably increases the vertical size or height of the package.
In view of the foregoing limitations, there is a need in the semiconductor art for an improved method for forming semiconductor packages of compact size (xe2x80x9cchip scale packagesxe2x80x9d or xe2x80x9cCSPsxe2x80x9d) approximating the length and width of the die itself and having a minimal number of component parts. Specifically, there is a need for an improved method for forming chip scale packages that have a uniform encapsulant extending from edge to edge of the active surface to provide a substantially hermetic seal across the entire active surface and over exposed edges of the layer or layers of integrated circuitry formed thereon. There is a further need for an improved method for forming a chip scale package that does not significantly complicate the manufacturing or handling of the integrated circuitry and that is repeatable and reliable when using conventional mass production manufacturing techniques. Preferably, the chip scale package could be substantially formed during and simultaneously with the fabrication of the die itself in wafer form.
The present invention includes a method of forming a semiconductor device by forming or providing a semiconductor wafer having an active surface defining a large plurality of individual die locations thereon. As used herein, the term xe2x80x9cwaferxe2x80x9d includes traditional wafer structures as well as silicon-on-insulator (SOI), silicon-on-glass (SOG) and silicon-on-sapphire (SOS) substrates, among other semiconductor substrates known in the art. The active surface of the semiconductor wafer includes bond pads thereon for making external electrical connections. Either the bond pads are provided with intermediate conductive elements thereon or the input/output connections provided by the bond pads are redistributed into a different pattern or array using traces over the active surface, and the intermediate conductive elements formed at the redistributed input/output locations. A grid of channels or troughs is formed, as by scribing with a wafer saw or etching, between die locations and of sufficient depth to pass through the active surface to an insulative region to isolate individual, adjacent die active surface regions on the semiconductor wafer. A flowable material used to encapsulate at least the active surface of the entire semiconductor wafer is applied thereto to cover the intermediate conductive elements and is then planarized to expose the intermediate conductive elements. The flowable encapsulant material extends into the channel regions, sealing the exposed, lateral edges of the active surface surrounding each individual die location. The intermediate conductive elements are then provided with external conductive elements projecting transversely from the surface of the encapsulant layer, or an anisotropically-conductive (so-called xe2x80x9cZ-axisxe2x80x9d) film may be placed over the substrate. Alternatively, conductive traces may be formed to extend between the exposed ends of the intermediate conductive elements and one or more edges of each die location to form one or more rows of edge connects suitable for DCA to a carrier substrate. The semiconductor wafer is cut through its entire depth, as with a wafer saw, along the centers of the channel regions to separate, or xe2x80x9csingulate,xe2x80x9d the individual die locations into flip-chip or DCA dice to be individually connected to a carrier substrate. Alternatively, the entire semiconductor substrate or a group of unsingulated dice may be mated to a carrier substrate and bonded thereto using the external conductive elements. As yet another alternative, the exposed ends of intermediate conductive elements alone may be employed as a land grid array for attachment of a die, substrate segment or entire semiconductor substrate to a bumped carrier substrate, and may optionally be provided with larger conductive pads thereover to facilitate connection to the carrier substrate bumps. As still another alternative, conductive traces can be extended from the bond pads across the active surface and down channel side walls between at least some of the individual die locations prior to encapsulation of the active surface of the semiconductor substrate, the trace ends then being exposed during singulation of the dice to form rows of electrical contacts along edges of the singulated dice, or groups of dice which remain together.